The present application relates to semiconductor technology, and more particularly to a semiconductor structure including a non-metal semiconductor alloy containing contact structure for an n-type field effect transistor (nFET) and a metal semiconductor alloy containing contact structure for a p-type field effect transistor (pFET) and a method of forming the same.
Field effect transistors (FETs) are the basic building block of today's integrated circuits. Such transistors can be formed in conventional bulk substrates (such as silicon) or in semiconductor-on-insulator (SOI) substrates.
State of the art FETs can be fabricated by depositing a gate conductor over a gate dielectric and a semiconductor substrate. Generally, the FET fabrication process implements lithography and etching processes to define the gate structures. After providing the gate structures, source/drain extensions are formed into a portion of the semiconductor substrate and on both sides of each gate structure by ion implantation. Sometimes this implant is performed using a spacer to create a specific distance between the gate structure and the implanted junction. In some instances, such as in the manufacture of an nFET device, the source/drain extensions for the nFET device are implanted with no spacer. For a pFET device, the source/drain extensions are typically implanted with a spacer present. A thicker spacer is typically formed after the source/drain extensions have been implanted. In some instances, deep source/drain implants can be performed with the thick spacer present. In other instances, and for advanced technologies, the source region and the drain region can be formed using a selective epitaxial growth process.
In prior art processes, source/drain metal semiconductor alloy contacts are formed on the source region and the drain region of both the nFET and the pFET devices. The formation of source/drain metal semiconductor alloy contacts on the surface of the source region and the drain region typically requires that a transition metal be deposited on the semiconductor substrate followed by a process to produce the metal semiconductor alloy. Such a process forms source/drain metal semiconductor alloy contacts to the deep source/drain regions of both the nFET and the pFET devices.
Metal semiconductor alloy contact resistance contributes to an ever larger portion of the total parasitic resistance in advanced complementary metal oxide semiconductor (CMOS) devices for current 20 nm and 14 nm technology nodes. Thus, there is a need for providing source/drain metal contacts in which the contact resistance is reduced. Moreover, there is a need for providing a source/drain metal contact that is beneficial for nFET devices, and another source/drain metal contact that is beneficial for pFET devices which can be readily co-integrated in one processing scheme.